1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device possessing a lightly doped drain (LDD) region. More particularly, the invention relates to a method of manufacturing a thin film transistor (TFT) possessing a gate electrode which is covered by an oxide film.
The invention further relates to a method of forming an insulated gate type semiconductor device which is formed on an insulating surface and possesses a silicon active layer in the form of a thin film and of forming an integrated circuit in which a large number of these devices are formed. The semi-conductor devices of the invention can be used as thin film transistors or integrated circuits of such transistors in the drive circuits of active matrices such as liquid crystal displays, etc. or image sensors, etc. or in SOI integrated circuits and conventional integrated circuits (microprocessors, microcontrollers, microcomputers and semiconductor memories, etc.). In the invention, insulating surface does not just mean the surface of an insulating substrate but also includes the surface of insulating films that are provided on semiconductors or conductors.
2. Description of the Related Art
In recent years, the formation of insulated gate semiconductor devices (or MOSFETs) on insulating surfaces has been tried. Such formation of semiconductor integrated circuits on insulating surfaces is advantageous in respect of high-speed drive of circuits, since, as opposed to conventional semiconductor integrated circuits in which the speed is mainly governed by the capacitance (stray capacitance) of the wiring and the substrate, this stray capacitance is not present on an insulating substrate. A MOSFET which is formed on an insulating substrate in this manner and possesses an active layer in the form of a thin film is called a thin film transistor (TFT). TFTs are essential for the purpose of raising the level of integration, and also for the purpose of forming integrated circuits as multilayer circuits. For example, TFTs are used as SRAM load transistors in semiconductor integrated circuits. It is also known to form TFTs for the purpose of driving active matrix type liquid crystal displays and image sensors, etc. In particular, because of the need for high-speed operation, crystalline silicon TFTs, with which mobility is higher, have recently been developed in place of amorphous silicon TFTs, in which amorphous silicon is used for the active layer.
If thin film transistors are to be used as drive elements in the individual pixel regions of an active matrix type liquid crystal display, it is necessary that the value of their off current be small. xe2x80x98Off currentxe2x80x99 is the current that flows between the source and drain even though the thin film transistor is in the xe2x80x98off statexe2x80x99. If the value of this off current is large, the charge held for a pixel falls, and it becomes impossible to maintain a screen display for a set time. The reason why off current occurs is that the thin film transistor constituting the active layer possesses a poly-crystalline structure or a microcrystalline structure.
For example, when an N-channel thin film transistor is in the off state, a negative voltage is imposed on the gate electrode. In this condition, the region of the channel-forming region which contacts the gate insulation film is P-type. Therefore, a PN junction is formed between the source and drain, and so hardly any current should flow. When, however, the active layer is constituted by a silicon film possessing a polycrystalline or a microcrystalline structure, migration of carriers (charges) via the crystal grain boundaries occurs, and this is the cause of off current.
An LDD (lightly doped drain) structure and an offset gate structure are known as structures for making this off current small. These are structures which are designed, mainly, to reduce the electric field strength at and in the vicinity of the interface of the channel-forming region and the drain region and thereby suppress migration of carriers via the crystal grain boundaries in this region.
However, in the case of TFTs, unlike the case with known semiconductor integrated circuit technology, there are still many problems that need to be solved, and there is the problem that it is difficult to produce required LDD structures or offset gate structures. In particular, when it is attempted to form a TFT on an insulating substrate such as a glass substrate, etc., there is the problem that, since the substrate becomes electrostatically charged, reactive ion anisotropic etching fails to function properly and etching therefore becomes unstable, and there is, for example, the problem that it is difficult to form fine patterns with good control.
FIG. 7 shows cross-sections of a typical LDD manufacturing process that has been employed hitherto. First, a base film 702 is formed on a substrate 701, and an active layer is formed with crystalline silicon 703. Then, an insulation film 704 is formed with material such as silicon oxide, etc. on this active layer. (FIG. 7(A))
Next, a gate electrode 705 is formed with polycrystalline silicon (doped with an impurity such as phosphorus, etc.), or with tantalum, titanium or aluminum, etc. Using this gate electrode as a mask, an impurity element (phosphorus or boron) is introduced by ion doping or a similar means, thereby forming, in a self-aligning manner in the active layer 703, lightly doped drain (LDD) regions 706 and 707 in which the dopant dose is small. The active layer region which is below the gate electrode and into which an impurity has not been introduced comes to constitute a channel-forming region. The impurity with which doping has been effected is then activated by a heat source such as a laser or a flashlamp, etc. (FIG. 7(B))
Next, an insulation film 708 of silicon oxide, etc. is formed by plasma CVD, LPCVD or a similar means (FIG. 7(C)), and anisotropic etching of this film is effected to form a sidewall 709 adjacent the side surface of the gate electrode. (FIG. 7(D))
Then, the impurity element is introduced again, by ion doping or a similar means, and, since the gate electrode 705 and sidewall 709 are used as a mask, regions (source/drain regions) 710 and 711 with quite a high impurity concentration are formed in a self-aligning manner in the active layer 703. The doping impurity is then activated by a heat source such as a laser or a flashlamp, etc.
Finally, a layer insulator 712 is formed, contact holes are formed going through the layer insulator to the source/drain regions, and wiring/electrodes 713 and 714 that connect to the source and drain are formed with metal material such as aluminum, etc. (FIG. 7(F)) Recently, products that require semiconductor integrated circuits to be formed on transparent insulating substrates have made an appearance. Examples are the drive circuits of optical devices such as liquid crystal displays and image sensors. TFTs are also used in these circuits. These circuits are required to be formed with a large surface area, and a reduction in the temperature of the TFT manufactory process is therefore required. Also, in cases where a device with a large number of terminals is on an insulating substrate and these terminals have to be connected to a semiconductor integrated circuit, consideration has been given to forming the actual semiconductor integrated circuit itself or its first stage monolithically on the same insulating substrate in order to reduce the packaging density.
Conventionally, a TFT is produced by annealing an amorphous, semi-amorphous or microcrystalline silicon film at a temperature of 450-1200xc2x0 C., to increase its crystallinity and improve it to a good-quality silicon film (ie, one with which mobility is sufficiently great), and using this as an active layer. There also exist amorphous silicon TFTs using amorphous silicon for the active layer, but the mobility in them is low, being 5 cm2/Vs, normally about 1 cm2/Vs, and considerations of operating speed, and also consideration of the fact that they do not permit production of P-channel TFTs mean that there are considerable restrictions on their use. Annealing at a temperature such as noted above is necessary in order to produce a TFT in which the mobility is 5 cm2/Vs. This annealing also makes it possible to produce a P-channel TFT (a PTFT).
Producing a high mobility TFT necessitates reducing the source/drain sheet resistance as well as that of the active layer. In particular, if the aim is to produce a TFT in which the field mobility exceeds 150 cm2/Vs, the sheet resistance must be 200 xcexa9/square, and, in view of this, a method using suicides for portions corresponding to the source/drain has been proposed.
FIG. 14 shows cross-sections of a typical currently devised TFT manufacturing process in which a silicide is used in order to reduce the sheet resistance of the portion corresponding to the source/drain section. First, a silicon active layer 1403 in the form of an island is formed on a substrate 1401. If required, a base film 1402 may be formed between the substrate and the active layer. Then, an insulation film 1404 that functions as a gate insulation film is formed with material such as silicon oxide, etc., on the active layer. (FIG. 14(A))
Next, a gate electrode 1405 is formed with poly-crystalline silicon (doped with an impurity such as phosphorus, etc. in order to lower the resistance), etc. Then, with this gate electrode as a mask, an impurity element (phosphorus or boron) is introduced by ion doping or a similar means, and impurity regions 1406 are formed in a self-aligning manner in the active layer 1403. The active layer region which is below the gate electrode and into which an impurity has not been introduced comes to constitute a channel-forming region. Then, the doping impurity is activated by thermal annealing, laser annealing, flashlamp annealing, rapid thermal annealing or a similar means. (FIG. 14(B))
Next, an insulation film 1407 of silicon oxide, etc. is formed by plasma CVD, LPCVD or a similar means (FIG. 14(C)), and a sidewall A1408 adjacent the side surface of the gate electrode is formed by anisotropic etching of this insulation film, by reactive ion etching or a similar means. (FIG. 14(D))
Then, a covering 1409 of a metal (eg, titanium, tungsten, molybdenum, platinum, or chromium, etc.) for forming a silicide over the whole surface is formed. (FIG. 14(E))
This is followed by thermal annealing, laser annealing or a similar means to react the metal covering 1409 and the impurity regions 1406 closely bonded thereto, and so form silicide regions 1410. At this time, the impurity region portions 1411 that are below the sidewall A1408 remain as impurity regions, since the metal covering 1409 is not formed on them. If silicon is used for the gate electrode, a silicide is also formed on the top surface of the gate electrode. On the other hand, the metal film deposited on the insulation film (silicon oxide, etc.) hardly reacts at all, and so a portion of the metal covering 1409 becomes a silicide, and the other portion thereof remains unreacted.
If, at this time, the ratio of the etching rates of the metal covering 1409 and its silicide is sufficiently great, it is possible to etch away only the unreacted metal covering. All the metals noted above are suitable for this purpose, since their etching rates are greater than those of their silicides. (FIG. 14(F))
Finally, a layer insulator 1412 is formed, contact holes going through the layer insulator to the source/drain regions are formed, and wiring/electrodes 1413 connecting to the source and drain are formed with metal material such as aluminum, etc. (FIG. 14(G))
In the element thus produced, the resistance of the silicide regions 1410 is much smaller than that of ordinary doped silicon doped with phosphorus or boron, and it can be effectively ignored. Therefore, what actually determines the source/drain sheet resistance is the width x of an impurity region 1411 below the sidewall, and since this is very small, it is possible to produce a TFT in which the source/drain sheet resistance is satisfactorily small.
The above method directly follows the procedure of a conventional LDD manufacturing process for semiconductor integrated circuits, and it comprises a stage which, if unmodified, is difficult to implement in manufacture of a TFT on a glass substrate, and stages which are undesirable in terms of productivity.
The difficulty lies in the formation of the sidewall. The thickness of the insulation films 708 and 1407 in FIG. 7 and FIG. 14 may be 0.5-2 xcexcm, and since the thickness of the base film 702 or 1402 provided on the substrate is normally 1000-3000 xc3x85, it often happens that a fall in the yield is caused due to the substrate being exposed because the base layer is etched by error in the etching stage. Such faults must be avoided as much as possible, since substrates, apart from synthetic quartz, that are used in TFT manufacture contain many elements that are harmful to silicon semiconductors. Further, it is also difficult to finish the sidewall to a uniform width. This is because fine control of the plasma in reactive ion etching (RIE) or similar plasma etching is difficult, since the substrate surface, unlike that of silicon substrates used in semiconductor integrated circuits, is insulating.
Further, because of their high resistance, the width of LDDs must be kept as small as possible, and an advance to mass production is difficult, because of the variability noted above, and the question of how to control a process for their self-alignment (ie, one in which positioning is effected without using a photolithographic method) constitutes a problem.
Another point is that, in the example shown in FIG. 14, when silicon is used for the gate electrode, a silicide is formed on the top surface of the gate electrode. However, when it is necessary to lower the gate electrode/wiring resistance (which applies, eg, in cases where the circuit size is large, and to liquid crystal displays, etc.), it is not always advantageous to use silicon for the gate electrode and it would be preferable to use metal material such as aluminum or titanium, etc., but there is the problem that even if such a metal is made a compound with the metal film 1409, it is not possible to effect selective etching, since the etching rate of the resulting compound does not differ greatly from that of the metal film 1409.
If, for example, aluminum is used for the gate electrode 1405, and titanium for the metal film 1409, titanium silicide is formed in the regions 1410. However, an aluminum/titanium alloy forms on the surface of the gate electrode. The titanium film can be etched by a mixed solution consisting of a hydrogen peroxide aqueous solution and ammonia, but the aluminum gate electrode is also etched at the same time. In other words, with the method of FIG. 14, the situation is that there is no choice but to use silicon or a silicide for the gate electrode, and this is a considerable obstacle to the reduction of the gate electrode""s resistance.
It is accordingly the object of the present invention to provide a method of forming a thin film transistor which resolves the above problems and which simplifies the process. More specifically, it has as its object to resolve at least one of the following aspects.
(1) The manufacture, with good control, of thin film transistors with an LDD structure.
(2) The provision of a method of manufacturing, with excellent productivity, thin film transistors with a small off current.
(3) The provision of thin film transistors whose off current is small.
(4) The provision of thin film transistors possessing characteristics that are not achieved with a conventional LDD structure or offset gate structure.
It is an aspect of the structure of a 1st invention disclosed in this specification that, in a TFT possessing a gate electrode covered by an oxide film, it comprises
a step in which the gate electrode is used as a mask, and an impurity at a low dose is introduced obliquely into a substrate, thereby forming low-concentration impurity regions in a self-aligning manner, and
a step in which an impurity at a high dose is introduced into the substrate from the vertical direction, thereby forming high-concentration impurity regions in a self-aligning manner,
wherein a lightly doped drain (LDD) region is formed below the oxide film.
A specific example of the above structure is shown in FIG. 3. The thin film transistor manufacturing stages shown in FIG. 3 are constituted as follows. In step (B), a gate electrode 306 covered by an oxide film 307 is formed. Then, using this gate electrode 306 and the oxide film 307 around it as a mask, impurity ions (in this case phosphorus ions) are implanted obliquely at a low dose in step (C), so forming low-concentration impurity regions 308. What is referred to here as a low dose is preferably a dose of 1xc3x971013-5xc3x971014 cmxe2x88x922.
Then, in step (D) the impurity is introduced at a high dose from the vertical direction, so forming high-concentration impurity regions 309. What is referred to here as a high dose is preferably a dose of 1014-5xc3x971015 cmxe2x88x922.
As a result of execution of step (D), low-concentration impurity regions can be formed in the active layer below the oxide film 307 that is around the gate electrode. The portion that is present on the drain side of these low-concentration impurity regions constitutes an LDD (lightly doped drain) region.
It is an aspect of the structure of a 2nd invention disclosed in this Specification that it comprises
an active layer,
a gate insulation film formed on this active layer, and
a gate electrode formed on this gate insulation film,
wherein an insulation layer in which the material constituting the gate electrode has been oxidized is formed on the side surface of the gate electrode,
and low-concentration impurity regions are formed in the active layer region corresponding to the portion below this insulation film.
The structure shown in FIG. 3 can be cited as a specific example of the above structure. The portion indicated by 304 in FIG. 3 is the active layer, which is an important element constituting a thin film transistor. 305 is the gate insulation film. 306 is the gate electrode, and 307 is the insulation layer, which is produced by oxidizing the gate electrode 306 in an anodic oxidation stage. 310 indicates low-concentration impurity regions. The portion on the drain region side functions as an LDD (lightly doped drain) region.
The arrangement in a 3rd invention is that
shield material provided around a gate electrode is taken as a mask, and
impurity ions are implanted obliquely into an active layer portion that corresponds to the portion below the shield material.
It is an aspect of a 4th invention that it comprises
an active layer,
a gate insulation film formed on this active layer, and
a gate electrode formed on this gate insulation film,
wherein an oxide covering in which the material constituting the gate electrode has been oxidized is formed on the side surface of the gate electrode,
low-concentration impurity regions are formed in the active layer region that corresponds to the portion below this oxide film,
and a metal layer is formed on the outer surface of the portions of the active layer region which constitute source and drain regions.
It is an aspect of the structure of a 5th invention that,
in a process for manufacturing a TFT possessing a gate electrode covered with an oxide covering, it comprises
a step in which the gate electrode is taken as a mask and an impurity is implanted obliquely into the substrate,
and a step in which a metal layer is formed on the outer surface of the active layer corresponding to the source and drain regions,
wherein, in the step in which the impurity is introduced, an impurity region is formed in the active layer below the oxide covering.
A 6th invention is a method of manufacturing which comprises at least the following 9 steps, in the indicated order.
(1) A step in which a silicon region in the form of an island is formed on an insulating surface,
(2) a step in which an insulation film that functions as a gate insulation film is formed on this silicon region,
(3) a step in which a gate electrode is formed on this insulation film,
(4) a step in which an anodic oxide is formed on the side surfaces and the top surface of this gate electrode
(5) a step in which, with the gate electrode and anodic oxide taken as a mask, the silicon region is irradiated, from an oblique direction, with accelerated impurity ions, and impurity regions (source and drain) are formed in a self-aligning manner,
(6) a step in which, with the gate electrode and anodic oxide taken as a mask, portions of the insulation film are removed, thereby exposing the upper surfaces of the impurity regions,
(7) a step in which a metal film is formed over the entire surface,
(8) a step in which the metal film and silicon are reacted, thereby forming silicide regions, and
(9) a step in which unreacted portions of the metal film are removed
A 7th invention is a method for manufacturing a semiconductor device which comprises at least the following 9 steps, in the indicated order.
(1) A step in which a silicon region in the form of an island is formed on an insulating surface,
(2) a step in which an insulation film that functions as a gate insulation film is formed on this silicon region,
(3) a step in which a gate electrode is formed on this insulation film,
(4) a step in which, with the gate electrode taken as a mask, the silicon region is irradiated, from an oblique direction, with accelerated impurity ions, and impurity regions (source and drain) are formed in a self-aligning manner,
(5) a step in which an anodic oxide is formed on the side surfaces and the top surface of the gate electrode,
(6) a step in which, with the gate electrode taken as a mask, portions of the insulation film are removed, thereby exposing the surfaces of the impurity regions,
(7) a step in which a metal film is formed over the entire surface,
(8) a step in which this metal film and silicon are reacted, thereby forming silicide regions, and
(9) a step in which unreacted portions of the metal film are removed.
An 8th invention is a method of manufacturing a semiconductor device which comprises at least the following 9 steps, in the indicated order,
(1) A step in which a silicon region in the form of an island is formed on an insulating surface,
(2) a step in which an insulation film that functions as a gate insulation film is formed on this silicon region,
(3) a step in which a gate electrode is formed on this insulation film,
(4) a step in which an anodic oxide is formed on the side surfaces and the top surface of this gate electrode,
(5) a step in which, with the gate electrode and anodic oxide taken as a mask, portions of the insulation film are removed and the surfaces of the impurity regions are exposed,
(6) a step in which a metal film is formed over the entire surface,
(7) a step in which, with the gate electrode and anodic oxide taken as a mask, the silicon region is irradiated, from a oblique direction, with accelerated impurity ions, and impurity regions (source and drain) are formed in a self-aligning manner,
(8) a step in which the metal film and silicon are reacted, thereby forming silicide regions, and
(9) a step in which unreacted portions of the metal film are removed.
A 9th invention is a method of manufacturing a semiconductor device which comprises at least the following 9 steps, in the indicated order.
(1) A step in which a silicon region in the form of an island is formed on an insulating surface,
(2) a step in which an insulation film that functions as a gate insulation film is formed on this silicon region,
(3) a step in which a gate electrode is formed on this insulation film,
(4) a step in which an anodic oxide is formed on the side surfaces and the top surface of this gate electrode,
(5) a step in which, with the gate electrode and anodic oxide taken as a mask, portions of the insulation film are removed and the surfaces of the impurity regions are exposed,
(6) a step in which a metal film is formed over the entire surface,
(7) a step in which the metal film and silicon are reacted, thereby forming silicide regions,
(8) a step in which the unreacted portions of the metal film are removed, and
(9) a step in which, with the gate electrode and anodic oxide taken as a mask, the silicon region is irradiated, from an oblique direction, with accelerated impurity ions and impurity regions (source and drain) are formed in a self-aligning manner.
It is a feature of the inventions disclosed in this Specification that use is made of an anodic oxide covering produced by anodic oxidation of a gate electrode. Another feature is that formation of impurity regions is effected by irradiating the substrate with accelerated impurity ions from an oblique direction. The procedure employed in this process may be that the substrate is rotated while held tilted relative to the direction of the ion source (rotation-tilt ion implantation method).
The apparatus shown in FIG. 1 is used for this rotation-tilt ion implantation. The apparatus shown in FIG. 1 comprises a chamber 101, a sample holder (substrate holder) 102 and an anode 103 inside this chamber, a power supply 104 for supplying a high voltage to the anode 103, and a grid electrode 105. The angle xcex8 of the sample holder 102 can be freely altered, so making it possible for ions to be injected obliquely. Also, the sample holder is provided with a rotation mechanism, and it can be rotated during ion implantation.
A voltage of up to a maximum of 100 kV is imposed on the anode 103. As a result of this high voltage, impurity ions 106 that are ionized by RF discharge, etc. in the vicinity of the grid electrode 105 are accelerated towards a substrate 107 (a sample) that is placed on the sample holder 102. Consequently, the accelerated impurity ions are implanted in the substrate.
A conceptual representation of this rotation-tilt ion implantation is shown in FIG. 2. As shown in FIG. 2(A), a TFT on a substrate mounted on the sample holder is held at an inclination xcex8 relative to the ions with which doping is effected. The depth in which the impurity is introduced is determined by this inclination xcex8. In the invention, it is preferable that this inclination xcex8 be 30 degrees or more. Since this angle xcex8 is maintained, doping to as far as the portion below the gate electrode is effected in the region indicated by 201.
In the region 202, however, since part of the region is in the shadow of the gate electrode, doping is effected only in the part which does not extend as far as the gate electrode. If, now, the sample holder is rotated 180 degrees, doping is also effected to as far as the portion underneath the gate electrode in region 201, as illustrated in FIG. 2(B). In this manner, ion doping at a low dose is effected. The arrangement in this case may be that the sample holder is rotated 180 degrees and doping is effected, but the same effect can be achieved more simply if doping is effected while the sample holder is being rotated. In this Specification, rotation-tilt ion implantation is represented in the manner shown in FIG. 2(C).
Effecting rotation-tilt ion implantation in this manner makes it possible for an impurity layer doped to a set penetration distance to be formed easily and uniformly.
In particular, to form a low-concentration impurity region (constituting a lightly doped drain (LDD) region), an impurity at a low dose is introduced obliquely. After first effecting ion doping at a low dose, ion doping at a high dose is effected. In this case, the impurity is injected from the direction that is normal to the TFT. With the arrangement made thus, no high-dose ion doping is effected and so a low-concentration impurity region is formed in the portion below the gate electrode in which low-dose ion doping was effected in the preceding stage.
It is noted that, in formation of a low-concentration impurity region in a thin film transistor possessing a gate electrode covered by an oxide covering film, by controlling the angle of incidence of the implanted impurity, it is possible to form a low-concentration impurity region only in the portion that is below the anodic oxide, and it is also possible to form a low-concentration impurity region that overlaps the channel-forming region.
It is thus both possible to form an LDD and possible to form an overlap LDD. What is meant here by xe2x80x98overlap LDDxe2x80x99 is a region which, like the LDD shown in FIG. 4, is the result of formation of an LDD region (indicated as 415) to as far as underneath the gate electrode. In other words, in the case of an overlap LDD, an LDD region is formed over a portion of the region which, conventionally, would constitute a channel-forming region.
It is also a feature of the invention that a low-concentration impurity region is formed by irradiating a substrate obliquely with impurity ions. In the method illustrated in FIG. 1, accelerated impurity ions are obliquely incident, coming from a specific direction relative to the substrate, but since the substrate is rotated, the ultimate result, regardless of what the direction relative to the substrate is, is oblique injection of ions. In this process, the distance to which the impurity is introduced is determined by the tilt angle xcex8 and the acceleration voltage. In the invention, the tilt angle xcex8 is preferably 30xc2x0 or more. Effecting rotation-tilt ion implantation in this manner makes it possible for a doped low-concentration impurity region to be formed easily and uniformly to a set penetration distance.
In general, when irradiation with impurity ions is effected obliquely, the distance to which the ions penetrate is determined by the ion acceleration voltage (or acceleration energy) and the penetration angle xcex8. In the invention, since the penetration angle xcex8 can be changed easily and the width of the impurity region can therefore be controlled very efficiently, the impurity region can be made such it overlaps the gate electrode (be brought to an overlap state) or be so formed that it is distant from the gate electrode (an offset state), as required. It is therefore possible to form an LDD only in the portion that is below the oxide, and it is also possible to form an overlap LDD that extends from underneath the gate electrode. Further, it is possible to make the impurity region and source/drain relation that of an overlap state or that of an offset state.
Since it is thus possible for the region constituting the low-concentration impurity region to be formed with a good control characteristic, it is possible to produce a thin film transistor possessing required characteristics (in particular, the off current characteristic).
Preferably, the metal covering that is for the purpose of forming a silicide in the invention is constituted by material that makes possible the formation of an ohmic or a close-to-ohmic, low-resistance contact with a silicon semiconductor. Specifically, molybdenum (Mo), tungsten (W), platinum (Pt), chromium (Cr), titanium (Ti) and cobalt (Co) are suitable. In practice in the invention, a silicide is produced by reacting at least one of these metals with silicon.
The anodic oxide plays an important role in connection with this in the invention. If material such as aluminum, titanium or tantalum, etc. is used for the gate electrode, the anodic oxide produced reacts hardly at all with the metals noted above, and so the metal covering deposited thereon remains practically unreacted. Further, the anodic oxide acts as an etching stopper during etching of the metal covering.
Therefore, after formation of a silicide, the metal covering can be removed without the gate electrode and other portions being etched and the silicide of the portions corresponding to the source and drain remains.
In the invention, the choice of the gate electrode material is important, since, among other things, it determines the type of anodic oxide that will be formed. A pure metal such as aluminum, titanium or tantalum or an alloy of such a metal containing a small amount of an additive (eg, an alloy in which 1-3% of silicon is added to aluminum) can be used for the gate electrode in the invention. It is noted that in this specification, unless otherwise specified, the term aluminum is taken to mean not just pure aluminum but also material containing 10% of an additive. The same also applies to titanium and other materials.
In the invention, use may be made of a gate electrode with a single-layer structure using one of the above materials alone, or the gate electrode may be a multilayer structure in which these materials are stacked in two or more layers. Examples are a two-layer structure in which titanium overlies aluminum, and a two-layer structure in which aluminum overlies titanium. The thickness of each layer is determined by the person practicing the invention in accordance with the required element characteristics.
FIG. 10 will be taken as an example to describe the effects and advantages of the above. The process of FIG. 10 is one that corresponds to the 6th invention described earlier. As shown in FIG. 10(A), a gate electrode 1005 is formed on an active layer 1003 on a substrate 1001 on which a base film 1002 is formed, and an anodic oxide 1006 is formed on the gate electrode""s top surface and side surfaces. (FIG. 10(A))
Next, oblique irradiation with an impurity is effected to form impurity regions 1007. As a result of this, the impurity regions also go round to underneath the anodic oxide 1006. (FIG. 10(B))
After that, an insulation film 1004 is etched, with the gate electrode and anodic oxide film serving as a mask. This etching etches away the portions of the silicon oxide film 1004 other than the silicon oxide film 1008 portion thereof that lies below the gate electrode and the anodic oxide. (FIG. 10(C)). Further, a metal covering 1009 for forming a silicide is deposited over the whole surface. (FIG. 10(D))
Then, the metal covering and impurity regions are reacted, so forming silicide regions 1011. However, the silicide reaction does not extend as far as the impurity region 1010 portions that are below the anodic oxide, and these portions therefore remain as impurity regions. Further, since the metal covering formed on the anodic oxide remains in a practically unreacted state, the unreacted portions of the metal film 1009 can be etched easily, and no etching of the gate electrode and other regions takes place.
In this manner, silicide regions 1011 and impurity regions 1010 are formed. Depending on how the silicide reaction progresses, the formation of the silicide may extend as far as the bottom of the active layer, as in FIG. 10(E), or may take place only on the surface of the active layer, as in FIG. 10(F). Naturally, in the former case, the sheet resistance of the portion corresponding to the source/drain is small, and in the latter case, too, the resistance is sufficiently low. In both cases, therefore, the source-drain sheet resistance is more or less determined by the impurity region 1010 width x.
The silicide thickness, which, too, is related to the above, is selected in accordance with the sheet resistance deemed necessary in the region corresponding to the source/drain. If it is required to achieve a sheet resistance of 10-100 xcexa9/square, this means that since the silicide""s resistivity is 0.1-1 mxcexa9xc2x7cm, the silicide thickness is suitably 100 xc3x85-1 xcexcm.
In formation of a silicide in the invention, the silicide may be produced by irradiating the metal film with a strong light such as a laser, etc. and causing reaction with the silicon semiconductor film that is underneath it. If a laser is used, a pulsed laser is preferable. With a continuous laser, there is a risk of peel-off due to expansion of the irradiated material caused by heat, and thermal damage of the substrate may occur, since the irradiation time is long.
By way of a pulsed laser, one may use an infrared laser such as an Nd:YAG laser (Q-switched pulse oscillation being preferred), or, by way of a 2nd harmonic thereof, a visible light laser, or various types of ultraviolet lasers using excimers such as KrF, XeCl and ArF, etc., but it is necessary to select a laser with a wavelength such that it is not reflected by the metal film when irradiation is effected from above the metal film. Basically, there is hardly any problem when the metal film is very thin. Irradiation with laser light may also be effected from the substrate side. In this case, it is necessary to select laser light that passes through the silicon semiconductor film that is present underneath.
FIG. 11 shows a further development of the process of FIG. 10. First, a base film 1102, an active layer 1103, an insulation film 1104 that functions as a gate insulation film, and a gate electrode 1105 that can be anodically oxidized are formed on a substrate 1101, and anodic oxidation of the top surface and the side surfaces of the gate electrode is effected, so producing an anodic oxide 1106. Then, with the gate electrode and the anodic oxide as a mask, impurity regions 1107 are produced in the active layer by oblique irradiation with impurity ions. The impurity concentration at this time is made lower than usual, and the dose is set at, for example, 1xc3x971013-5xc3x971014 atoms/cm2. (FIG. 11(A))
Next, impurity regions 1108 are formed by irradiation with ions of the same conduction type from the generally vertical direction, with the impurity concentration greater than that of the previously formed impurity regions 1107. The dose in this case is suitably 1xc3x971014-5xc3x971015 atoms/cm2. As a result of this, low-concentration impurity regions 1109 are formed below the anodic oxide film. (FIG. 11(B))
Then, with the gate electrode and anodic oxide as a mask, the insulation film 1104 is etched, and a metal covering 1110 is deposited over the whole surface (FIG. 11(C))
Then, the metal covering and the impurity regions are reacted, and silicide regions 1112 are formed. However, the silicide reaction does not extend as far as the impurity region 1109 portions that are below the anodic oxide, and these portions therefore remain as impurity regions. Since the metal covering formed on the anodic oxide remains in a practically unreacted state, the unreacted portions of the metal covering 1110 can be etched easily, and no etching of the gate electrode or other regions takes place.
In this manner, silicide regions 1112 are formed. Depending on how the silicide reaction progresses, the formation of a silicide may extend as far as the bottom of the active layer, as in FIG. 11(D), or may take place only on the surface of the active layer, as in FIG. 11(E). The type of formation should be selected in accordance with the requirements of the person practicing the invention.
After that, an interlayer insulator 1113 is deposited, contact holes are formed in the silicide regions, and metal wiring-electrodes are formed. Once this is done, the TFT is completed.
In the example of FIG. 11, doping with an impurity at low concentration was effected for the source/drain regions. In an ordinary TFT, when doping with an impurity at low concentration is effected in this manner, the field in the vicinity of the drain is eased, deterioration due to hot carrier injection is reduced and source-drain leakage current is also reduced, but in a device as in, eg, FIG. 10 in which the impurity regions 1007 are low-concentration regions, because the impurity concentration is low, the source-drain leakage current is liable to increase when the drain voltage is high, since the NI junction (PI junction in the case of a P-channel TFT) is thin and the distance between the silicide regions is short. High-concentration doping as in FIG. 11 is an effective way of preventing this.
FIG. 10 and FIG. 11 are drawings illustrating stages in the 6th invention, and, needless to say, similar effects and advantages are also achieved in the other inventions.